• Core

  Cortex-M0, 48 MHz

• Family

  M0 Series

• Sub-Family

  CMS32 Series

• CMSIS Pack

  CMS32-Series

Core
- ARM Cortex-M0 core runs up to 48 MHz
- One 24-bit system timer
- Supports low power Sleep/Deep sleep/Stop Mode
- A single-cycle 32-bit hardware multiplier
- A six-cycles 32-bit hardware divider
Memory
- 32KB Flash memory for program memory and boot
- Independent 1KB Flash memory for data memory
- 8KB SRAM for internal scratch-pad RAM (SRAM)
In-System Programming (ISP) & In-Application Programming (IAP) & In-Circuit Programming (ICP)
Clock Control
- Programmable system clock source
- 48 MHz internal oscillator (HIRC) (1% accuracy at 25'C, 2.1 V to 5.5 V)
- 40 KHz internal low-power oscillator (LIRC) for watchdog and idle wakeup
I/O Port
- Up to 30 General Purpose I/O (GPIO) pins
Timer
- Two 16/32-bit Timers with 3-levels pre-scaler
Watchdog Timer & Window Watchdog Timer
- Programmable clock source and timeout period
EPWM
- Built-in enhanced PWM, up to six channels
CCP
- Two groups CCP(Capture/Compare/PWM)
UART
- Two UART devices
SPI
- One SPI device
I2C
- One I2C device
ADC1
- 12-bit SAR ADC with 1.2MSPS
Analog Comparator
- Two analog comparators
Operation Amplifier
- Two operation amplifiers
LVR
- Programmable 3 threshold levels: 1.9V/2.1V/2.6V
LVD
- Programmable 6 threshold levels: 2.0V/2.2V/2.4V/2.7V/3.0V/3.7V
96-bit unique ID
128-bit user ID