• Core

  Cortex-R7, 12 MHz

• Family

  ARM Cortex R7

• CMSIS Pack

  Cortex_DFP

The Cortex-R7 processor features an 11-stage, superscalar, out-of-order pipeline with dynamic and static branch prediction, dynamic register re-naming and non-blocking Load-Store Unit. There is also an integrated Generic Interrupt Controller (GIC), Snoop Control Unit (SCU) and timers to further reduce latency and enable symmetric multiprocessing in a dual core configuration.