The CADC continuous EDMA demo application demonstrates the usage of the ADC and EDMA peripheral while in a Loop Sequential mode. TheCADC is first set to Loop Sequential mode. In Loop Sequential convert configuration, only the initial rising-edge to launch continuous conversions isobserved, and until conversion is aborted, the CADC continues to do conversions on the same CLIST register that initiated the conversion. EDMA request will be asserted during an CADC conversion READY event noted when any of the ADC_RDY[RDYn] flags is asserted. EDMA will transferCADC results to memory and if users press any key, demo will average CADC results stored in memory and print average on the terminal.

The cadc_dual_parallel_conversion example shows how to use the both converter parallel at the same time with CADC driver.In this example, the CADC is configured as "kCADC_DualConverterWorkAsTriggeredParallel" (default) work mode. User shouldindicate 4 channel pairs to provide the differential voltage signal (can be controlled by user) as the inputs for CADCsample slots. These sample slots would be assembled into the two conversion sequence for each converter. In "kCADC_DualConverterWorkAsTriggeredParallel" mode, the converter A converts sample 0 and sample 1 (sample 0-7 areavailable) and the converter B converts sample 8 and sample 9 (sample 8-15 are available). As the "simultaneous mode" isenabled by default, the converter A's control logic can operate both the two converters, to start and stop together.When running the project, typing any key into debug console would trigger the conversion. And then, the conversion result data of the four sample slots (Sample 0, 1, 8, 9) would be displayed in the terminal.

The cadc_dual_seperate_conversion example shows how to use each converter separately with CADC driver.In this example, the CADC is configured as "kCADC_DualConverterWorkAsTriggeredParallel" work mode. User should indicate4 channel pairs to provide the differential voltage signal (can be controlled by user) as the inputs for CADC sample slots. These sample slots would be assembled into the two short conversion sequences (can include 8 sample slots as most). Also the "simultaneous mode" is disabled, so that each converter can be operated by their own control logic separately.When running the project, typing any key into debug console would trigger the conversion. And then, the conversion result data of the converter A's sample slots (Sample 0, 1) would be displayed in the terminal. Type the keyboard againto trigger the converter B, the conversion result data of the converter B's two sample slots (Sample 8, 9) would be displayed.

This is an CADC demo application which shows how to use hardware trigger sources to handlethe CADC hardware trigger function. The Low Power Timer (LPTMR) is a period timer source and the CADChardware trigger event. Because the LPTMR trigger event can be used to trigger one of the CADC ,this demo uses the LPTMR as a trigger source for a CADCx channel. The LPTMR triggers the CADC in afixed frequency and the demo gets the CADC conversion result in the CADC Conversion Complete (COCO) interrupt.This demo uses DAC fifo to generate sinewave on DACx_OUT.

This is an CADC demo application which shows how to use hardware trigger sources to handlethe CADC hardware trigger function. The Programmable Delay Block (PDB) is a period timer source and the CADChardware trigger event. Because the PDB trigger event can be used to trigger one of the CADC ,this demo uses the PDB as a trigger source for a CADCx channel. The PDB triggers the CADC in afixed frequency and the demo gets the CADC conversion result in the CADC Conversion Complete (COCO) interrupt.This demo uses DAC fifo to generate sinewave on DACx_OUT.

This is an CADC demo application which shows how to use hardware trigger sources to handlethe CADC hardware trigger function. The Periodic Interrupt Timer (PIT) is a period timer source and the CADChardware trigger event. Because the PIT trigger event can be used to trigger one of the CADC ,this demo uses the PIT as a trigger source for a CADCx channel. The PIT triggers the CADC in afixed frequency and the demo gets the CADC conversion result in the CADC Conversion Complete (COCO) interrupt.This demo uses DAC fifo to generate sinewave on DACx_OUT.

This is an CADC demo application which shows how to use hardware trigger sources to handlethe CADC hardware trigger function. The Pulse Width Modulator (PWM) is a period timer source and the CADChardware trigger event. Because the PWM trigger event can be used to trigger one of the CADC ,this demo uses the PWM as a trigger source for a CADCx channel. The PWM triggers the CADC in afixed frequency and the demo gets the CADC conversion result in the CADC Conversion Complete (COCO) interrupt.This demo uses DAC fifo to generate sinewave on DACx_OUT.

The cadc_sequential_conversion example shows how to use a long conversion sequence (can include as many as all the 16 sample slots) with CADC driver.In this example, the CADC is configured as "kCADC_DualConverterWorkAsTriggeredSequential" work mode. User should indicate 4 channel pairs to provide the differential voltage signal (can be controlled by user) as the inputs for CADCsample slots. These sample slots would be assembled into a long conversion sequence.In "kCADC_DualConverterWorkAsTriggeredSequential" mode, all the sample slots are organized as a long conversion sequence. The converter A's control logic would be used to operate this long conversion sequence. It can start and stopthe sequence.When running the project, typing any key into debug console would trigger the conversion. And then, the conversion result data of the four sample slots (Sample 0, 1, 2, 3) would be displayed in the terminal.

The CMP interrupt Example shows how to use interrupt with CMP driver.In this example, user should indicate an input channel to capture a voltage signal (can be controlled by user) as the CMP's positive channel input. On the negative side, the internal 6-bit DAC is used to generate the fixed voltage abouthalf value of reference voltage.When running the project, change the input voltage of user-defined channel, then the comparator's output would changebetween logic one and zero when the user-defined channel's voltage crosses the internal DAC's value. The change ofcomparator's output would generate the falling and rising edge events with their interrupts enabled. When any CMP interrupt happens, the CMP's ISR would turn on the LED light if detecting the output's rising edge, or turn off it whendetecting the output's falling edge.

The CMP polling Example shows the simplest way to use CMP driver and help user with a quick start.In this example, user should indicate an input channel to capture a voltage signal (can be controlled by user) as the CMP's positive channel input. On the negative side, the internal 6-bit DAC is used to generate the fixed voltage abouthalf value of reference voltage.When running the project, change the input voltage of user-defined channel, then the comparator's output would changebetween logic one and zero when the user's voltage crosses the internal DAC's value. The endless loop in main() functionwould detect the logic value of comparator's output, and change the LED. The LED would be turned on when the compareoutput is logic one, or turned off when zero.